"Although, what does CMB_PHYA_OFFSET3 mean?"
answer:
the function sunxi_mipi_subdev_s_stream(..) has the following function calls:
mipi->pyha_offset it is the CMB_PHYA_OFFSET3 argument! and it is passed to the function combo_rx_init(sd); and then to the func. cmb_rx_phya_offset(mipi->id, mipi->pyha_offset);
void cmb_rx_phya_offset(unsigned int sel, unsigned int offset)
{
vin_reg_clr_set(cmb_rx_base_addr[sel] + CMB_PHYA_CTR_REG_OFF,
CMB_PHYA_OFFSET_SEL_MASK, offset << CMB_PHYA_OFFSET_SEL); /*mipi 3, lvds 0*/
}
But V5 manual does not contain descriptions of mipi registers (((
may be Lindenis will help us ??? ))
answer:
the function sunxi_mipi_subdev_s_stream(..) has the following function calls:
Code:
mipi->cmb_mode = res->res_combo_mode & 0xf;
mipi->terminal_resistance = res->res_combo_mode & CMB_TERMINAL_RES;
mipi->pyha_offset = (res->res_combo_mode & 0x70) >> 4;
if (enable) {
combo_rx_init(sd);
bsp_mipi_csi_dphy_init(mipi->id);
bsp_mipi_csi_set_para(mipi->id, &mipi->csi2_cfg);
bsp_mipi_csi_set_fmt(mipi->id, mipi->csi2_cfg.total_rx_ch, &mipi->csi2_fmt);
/*for dphy clock async*/
bsp_mipi_csi_dphy_disable(mipi->id);
bsp_mipi_csi_dphy_enable(mipi->id);
bsp_mipi_csi_protocol_enable(mipi->id);
} else ....
mipi->pyha_offset it is the CMB_PHYA_OFFSET3 argument! and it is passed to the function combo_rx_init(sd); and then to the func. cmb_rx_phya_offset(mipi->id, mipi->pyha_offset);
void cmb_rx_phya_offset(unsigned int sel, unsigned int offset)
{
vin_reg_clr_set(cmb_rx_base_addr[sel] + CMB_PHYA_CTR_REG_OFF,
CMB_PHYA_OFFSET_SEL_MASK, offset << CMB_PHYA_OFFSET_SEL); /*mipi 3, lvds 0*/
}
But V5 manual does not contain descriptions of mipi registers (((
may be Lindenis will help us ??? ))